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JTAG Pin constraints in VC707


We are trying to implement ARC EM6 processor with JTAG interface on VC707 Evaluation board.

In this design we want to connect JTAG connection from ARC EM6 processor to JTAG pins of FPGA.

we are unable to find the pin locations of JTAG.

Can any one help us.



  • Hi Prakash,
    May I ask what you mean by "pin locations of JTAG"? If it's for your VC707 board your question seems to be more targeted at the evaluation board rather than ARC.
    What is clear is that if you've configured ARC to have JTAG ports and debug ports, when you connect HS2 cable to the JTAG pins of ARC core, Metaware would recognize the processor and you'll be able to halt/run/debug code running on ARC on the FPGA. So please ask Xilinx for more information or read their related doc if you want to multiplex the jtag pins of the VC707 board.
    Thanks and regards.
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